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april 2006 rev 3 1/53 1 M65KA128AL 128mbit (4 banks x 2m x 16) 1.8v supply, low power sdrams feature summary 128mbit synchronous dynamic ram ? organized as 4 banks of 2 mwords, each 16 bits wide supply voltage ?v dd = 1.65v to 1.95v ?v ddq = 1.65 to 1.95v for input/output synchronous burst read and write ? fixed burst lengths: 1, 2, 4, 8 words or full page ? burst types: sequential and interleaved. ? maximum clock frequency: 104mhz ?cas latency 2, 3 automatic precharge low power features: ? pasr (partial array self refresh), ? automatic tcsr (temperature compensated self refresh) ? driver strength (ds) ? deep power-down mode delivery form: unsawn wafer auto refresh and self refresh lvcmos interface compatible with multiplexed addressing operating temperature ? ?25c to +90c the M65KA128AL is only available as part of a multi-chip package product. wafer www.st.com
contents M65KA128AL 2/53 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 address inputs (a0-a11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 bank select inputs (ba0-ba1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 data inputs/outputs (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 chip select (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 column address strobe (cas) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 row address strobe (ras) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 write enable (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 clock input (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 clock enable (ke) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 lower/upper data input/output mask (ldqm/udqm) . . . . . . . . . . . . . . 10 2.11 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.12 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.13 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.14 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 deep power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 mode register set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 extended mode register set command . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 bank (row) activate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M65KA128AL contents 3/53 4.5 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 auto precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 burst terminate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.9 data mask command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.10 clock suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.11 power-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.12 auto refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.13 self refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.14 deep power-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 extended mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
list of tables M65KA128AL 4/53 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. extended mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. dc characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. dc characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. self refresh current (i dd6 ) values in normal operating mode . . . . . . . . . . . . . . . . . . . . . 25 table 13. synchronous ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. asynchronous ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 16. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
M65KA128AL list of figures 5/53 list of figures figure 1. logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. ac measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 figure 4. chip enable signal during read, write and precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5. read with precharge ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 6. read with auto precharge ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 7. clock suspend during burst read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8. random column read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. random row read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10. column interleaved read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11. burst column read followed by auto precharge ac waveforms . . . . . . . . . . . . . . . . . . . 35 figure 12. write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13. byte write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 14. mode register set ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 figure 15. clock suspend during burst write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16. random column write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17. random row write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 18. column interleaved write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 19. burst column write followed by auto precharge ac waveforms . . . . . . . . . . . . . . . . . . . 43 figure 20. precharge termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21. power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 22. power-down mode and clock masking ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 23. auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 24. self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 25. deep power-down entry ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 26. deep power-down exit ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
summary description M65KA128AL 6/53 1 summary description the M65KA128AL is a 128 mbit low power synchronous dram (sdram) organized as 4 banks of 2,097,152 words of 16 bits each. the low power sdram achieves low power consumption and high-speed data transfer using the pipeline architecture. it is well suited for handheld battery powered applications like pdas, 2.5 and 3g mobile phones and handheld computers. the device architecture is illustrated in figure 2: functional block diagram . the device uses burst mode to read and write data. it is capable of one, two, four, eight-word and full page, sequential and interleaved burst. to minimize current consumption during self-refresh operations, the M65KA128AL includes three system-accessible mechanisms configured via the extended mode register: automatic temperature compensated self refresh (tcsr) is used to adapts the refresh rate according to the operating temperature. partial array self refresh (pasr) performs a limited refresh of a half bank, a quarter of bank, one bank, two banks or all banks. the deep power-down (dpd) mode completely halts the refresh operation and achieves minimum current consumption by cutting off the supply voltage from the whole memory array. the M65KA128AL is programmable through two registers, the mode register and the extended mode register: the mode register is used to select the cas latency, the burst type (sequential or interleaved) and the burst length. for more details, refer to table 4: mode register definition , and to section 4.1: mode register set command . the extended mode register is used to program the low power features (pasr and driver strength) to reduce the current consumption during the self refresh operations. for more details, refer to table 5: extended mode register definition , and to section 4.2: extended mode register set command . the M65KA128AL is offered in unsawn wafer.
M65KA128AL summary description 7/53 figure 1. logic diagram table 1. signal names a0-a11 address inputs ba0-ba1 bank select inputs dq0-dq15 data inputs/outputs k clock input ke clock enable input e chip select input w write enable input ras row address strobe input cas column address strobe input udqm upper data input/output mask ldqm lower data input/output mask v dd supply voltage v ddq input/output supply voltage v ss ground v ssq input/output ground ai12138 12 a0-a11 dq0-dq15 v dd M65KA128AL e cas v ss 16 ras v ddq ba0-ba1 2 k ke w v ssq udqm ldqm
summary description M65KA128AL 8/53 figure 2. functional block diagram extended mode register pasr self refresh logic & timer internal row counter row pre- decoders k ke e ras cas w udqm state machine refresh column active bank select address registers address buffers 2 m x 16 bank 3 2 m x 16 bank 2 2 m x 16 bank 1 2 m x 16 bank 0 row decoders row decoders row decoders row decoders memory cell array column decoders sense amp & i/o gate i/o buffer & logic dq0 dq15 ... ... ... column pre- decoders column add counter mode register cas latency data out control burst counter burst length ai08974d row active a0-a11/ba0-ba1 ldqm
M65KA128AL signal descriptions 9/53 2 signal descriptions see figure 1: logic diagram , and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a11) the a0-a11 address inputs are used to select the row or column to be made active. if a row is selected, all a0-a11 address inputs are used. if a column is selected, only the nine least significant address inputs, a0-a8, are used. in this latter case, a10 determines whether auto precharge is used. if a10 is high (set to ?1?) during read or write, the read or write operation includes an auto precharge cycle. if a10 is low (set to ?0?) during read or write, the read or write cycle does not include an auto precharge cycle. 2.2 bank select inputs (ba0-ba1) the ba0 and ba1 banks select inputs are used to select the bank to be made active. the device must be enabled, the row address strobe, ras , must be low, v il , the column address strobe, cas , and w must be high, v ih , when selecting the addresses. the address inputs are latched on the rising edge of the clock signal, k. 2.3 data inputs/outputs (dq0-dq15) the data inputs/outputs output the data stored at the selected address during a read operation, or are used to input the data during a write operation. 2.4 chip select (e ) the chip select input e activates the memory state machine, address buffers and decoders when driven low, v il . when high, v ih , the device is not selected. 2.5 column address strobe (cas ) the column address strobe, cas , is used in conjunction with address inputs a8-a0 and ba1-ba0, to select the starting column location prior to a read or write. 2.6 row address strobe (ras ) the row address strobe, ras , is used in conjunction with address inputs a11-a0 and ba1-ba0, to select the starting address location prior to a read or write. 2.7 write enable (w ) the write enable input, w , controls writing.
signal descriptions M65KA128AL 10/53 2.8 clock input (k) the clock signal, k, is used to clock the read and write cycles. during normal operation, the clock enable pin, ke, is high, v ih . the clock signal k can be suspended to switch the device to the self refresh, power-down or deep power-down mode by driving ke low, v il . 2.9 clock enable (ke) the clock enable, ke, pin is used to control the synchronizing of the signals to clock signal k. the signals are clocked when ke is high, v ih when ke is low, v il , the signals are no longer clocked and data read and write cycles are extended. ke is also involved in switching the device to the self refresh, power-down and deep power-down modes. 2.10 lower/upper data input/output mask (ldqm/udqm) lower data input/output mask and upper data input/output mask pins are input signals used to control the input and output buffers, respectively. during read operations, ldqm and udqm control the output buffer. when both ldqm and udqm are high, v ih , the output buffer is disabled. when held low, v il , the output buffer is enabled. ldqm and udqm are used to mask the data read or written from or to the memory array. ldqm low, v il , gates the data from or to the lower byte data i/o (dq0 to dq7) while udqm low, gates the data from or to the upper byte data i/os (dq8 to dq15). during read operations, the latency between ldqm/udqm high or low and data output disabled or enabled is two clock cycles. during write operations, there is no latency between ldqm/udqm stable and data input valid. 2.11 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read and write). 2.12 v ddq supply voltage v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently of v dd . v ddq can be tied to v dd or can use a separate supply. it is recommended to power-up and power-down v dd and v ddq together to avoid certain conditions that would result in data corruption. 2.13 v ss ground ground, v ss, is the reference for the core power supply. it must be connected to the system ground.
M65KA128AL signal descriptions 11/53 2.14 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss . note: each device in a system should have v dd and v ddq decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package).
operations M65KA128AL 12/53 3 operations there are 7 operating modes that control the memory. each of these is described in this section, see table 2: operating modes , for a summary. 3.1 power-up the low power sdram has to be powered up and initialized in a well determined manner: 1. power must be applied to v dd and v ddq simultaneously. 2. after applying v dd and vd dq , a minimum pause of 200s must be respected before the signals can be toggled. 3. the precharge command must then be issued to all banks. the clock enable input, ke, and udqm/ldqm must be held high until the precharge command is issued to make sure that dq0-dq15 remain high impedance. 4. t rp after precharging all the banks, the mode register and the extended mode register must be set by issuing a mode register set command and an extended mode register set command, respectively. a minimum pause of t mrd must be respected after each register set command. 5. after configuring the registers, 2 or more auto refresh cycles must be executed before the device is ready for normal operation. the fourth and fifth steps can be swapped. 3.2 burst read the read command is used to switch the device to burst read mode (see section 4.4: read command for details). in burst read mode the data is output in bursts synchronized with the clock. a valid burst read operation is initiated by driving e and cas low, v il , and by driving w and ras high, v ih , at the positive edge of the clock signal, k. burst read can be accompanied by an auto precharge cycle depending on the state of the a10 address input. if a10 is high (set to ?1?) when the burst read command is issued, the burst read operation will be followed by an auto precharge cycle. during burst read operation, the memory reads data from the activated bank. different burst types and lengths can be programmed using the mode register bits (see section 5.1: mode register description ). the burst types available are sequential and interleaved, selected using mode register bit a3. possible burst lengths are 1-, 2-, 4-, 8- word and full page, selected using mode register bits a2 to a0.
M65KA128AL operations 13/53 3.3 burst write the write command is used to switch the device to burst write mode (see section 4.5: write command for details). in burst write mode the data is input in bursts synchronized with the clock. a valid burst write is initiated by driving e , cas and w low, v il , and by driving ras high, v ih , at the positive edge of the clock signal, k. burst write can be accompanied by an auto precharge cycle depending on the state of the a10 address input. if a10 is high (set to ?1?) when the write command is issued, the write operation will be followed by an auto precharge cycle. during burst write operation, the memory writes data to the activated bank. as for burst read, different burst types and lengths can be utilized, programmed in the same fashion. 3.4 self refresh in self refresh mode, the data contained in the low power sdram memory array is retained and refreshed. the low power sdram refresh cycles are asynchronous. the self-refresh mode is entered by driving ke low (set to ?0?), with e , ras , and cas low, and w high (set to ?1?). when in this mode, the device is not clocked any more. the self refresh mode is exited by driving ke from low to high, with e high, ras , cas and w don?t care, or with e low and r as , cas and w high. 3.5 auto refresh the auto refresh mode is used to refresh the low power sdram in normal operation mode whenever needed. during an auto refresh operation, ke must be kept high, v ih and the address bits are ?don?t care? because the specific address bits are generated by the internal refresh address counter. 3.6 power-down in power-down mode, the current is reduced the standby current. for the memory to enter the power-down mode, ke must be held low (set to ?0?), after the precharge time t rp , with e high (set to ?1?), ras , cas and w don?t care, or with e low, ras , cas and w high. the power-down mode is exited by driving ke high, with e high, ras , cas and w don?t care, or with e low and ras , cas and w high.
operations M65KA128AL 14/53 3.7 deep power-down the purpose of this mode is to achieve maximum power reduction by cutting the power supply to the whole memory array. data is no longer retained when the device enters deep power-down mode. the low power sdram is switched to deep power-down mode by applying v il to e and w , and v ih to ras and cas on the rising edge of the clock, k, and by driving ke low, v il . for more information, see figure 25: deep power-down entry ac waveforms . the low power sdram is released from deep power-down mode by applying v ih to ke, with all other pins don?t care. then a special sequence, is required before the device can take any new command into account: 1. maintain no operation status conditions (see ta b l e 3 for a minimum time of 200s, 2. issue a precharge command to all the banks of the device (see section 4.6: precharge command for details), 3. issue 2 or more auto-refresh commands, 4. issue a mode register set command and an extended mode register set command to initialize the mode register and the extended mode register, respectively. the third and fourth steps can be swapped. the deep power-down mode exit sequence is illustrated in figure 26: deep power-down exit ac waveforms . table 2. operating modes (1) operating mode ken-1 ken e ras cas w a10 a9, a11 a0-a7 ba0-ba1 burst read v ih xv il v ih v il v ih v il valid start column address bank select burst write v ih xv il v ih v il v il v il valid start column address bank select self refresh v ih v il v il v il v il v ih xx auto refresh v ih v ih v il v il v il v ih xx power-down v ih v il v il v ih v ih v ih xx v ih xxx deep power-down v ih v il v il v ih v ih v il xx device deselect v ih xv ih xxxxx x x no operation v ih xv il v ih v ih v ih x 1. x = don?t care v il or v ih .
M65KA128AL commands 15/53 4 commands there are 16 commands that control the memory. refer to table 3: commands , in conjunction with the text descriptions below and to table 3: commands . 4.1 mode register set command the mode register set command is issued by applying v il to e , ras , cas and w and by setting ba1 to ?0?, and ba0 to ?0?. the mode register set command must be executed after the power-up sequence prior to issuing a bank (row) active command. the execution of a mode register set command will re-program the mode register, modifying its contents. 4.2 extended mode register set command the extended mode register set command is issued by applying v il to e , ras , cas and w , and then by setting ba1 to ?1?, and ba0 to ?0?. the extended mode register set command must be executed after the power-up sequence prior to issuing a bank (row) active command. the execution of an extended mode register set command will re-program the extended mode register, modifying its contents. 4.3 bank (row) activate command the bank (row) active command is used to activate a row in a specific bank of the device. this command is initiated by driving e and ras low, v il , and driving cas and w high, v ih , at the positive edge of the clock signal, k. the value on ba1 and ba0 selects the bank, and the value on a0-a11 selects the row. the selected row remains active for column access until a precharge command is issued to the bank containing the row. a minimum time of t rcd is required after issuing the bank (row) active command prior to initiating read and write operations from and to the activated bank.
commands M65KA128AL 16/53 4.4 read command the read command is used to switch the low power sdram to burst read mode (see section 3.2: burst read ). during burst read operation, the memory reads data from the activated bank. inputs ba1 and ba0 are used to select a bank, address inputs a8-a0 are used to select a starting column location. the value at input a10 determines whether auto precharge is activated. if auto precharge is selected, the row being accessed will be precharged at the end of the burst read operation. if auto precharge is not selected, the row will remain active for subsequent accesses. different burst types and lengths can be programmed using the mode register bits (see table 4: mode register definition ): the burst types available are sequential and interleaved selected using mode register bit mr3. possible burst lengths are 1-, 2-, 4-, 8-word and full page, selected using mode register bits mr0 to mr2. 4.5 write command the write command is used to switch the low power sdram to burst write mode (see section 3.3: burst write ). during burst write operation, the memory writes data to the activated bank. inputs ba1 and ba0 inputs are used to select a bank, the a8-a0 address inputs are used to select a starting column location. the value at the a10 input determines whether auto precharge is activated. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst. if auto precharge is not selected, the row will remain active for subsequent accesses. burst types and lengths apply to burst write operation in the same manner as they do to burst read operations. 4.6 precharge command the precharge command is used to close the open row in a particular bank, or the open rows in all the banks, depending on the value on the a10 address input. if a10 is high, at v ih , when the precharge command is issued, the command will be applied to all the banks, closing all the open rows in these banks. if a10 is low, at v il , when the precharge command is issued, the command will be applied only to the selected bank, closing the open row of this bank. the precharge command can also be used to terminate a burst. issued during a burst read or burst write cycle, the precharge command will interrupt the burst operation and close the active bank. the precharge command can be issued any time after t ras min. is satisfied. soon after the precharge command is issued, the precharge operation performed and the synchronous dram enters the idle state after t rp is satisfied. the t rp parameter is the time required to perform the precharge. the earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is cl-1 clock cycles before the reference clock that indicates the last data word is valid (see figure 5 )
M65KA128AL commands 17/53 in order to write all data to the memory cell correctly, the asynchronous parameter t dpl must be satisfied. the t dpl (min.) specification defines the earliest time that a precharge command can be issued. after the precharge command is issued, a minimum time of t rp is required before the bank(s) are available. 4.7 auto precharge command the auto precharge command is used to close the open row in a specific bank after a read or write cycle. read or write with auto precharge is initiated if the a10 address input is high, at v ih , when a read or write command is issued. 4.8 burst terminate command the burst terminate command is used to terminate a burst operation. a burst operation can be interrupted by using the precharge command (see the section 4.6: precharge command for details), or by issuing the burst terminate command. issuing the burst terminate command during a burst read or write cycle will terminate the burst while leaving the bank open. 4.9 data mask command the data mask command is used to mask the read or write data. a data mask command issued during a read cycle will disable the data outputs, switching them to the high- impedance state after a delay of two clock cycles. a data mask command issued during a write cycle will disable the data inputs with no delay. 4.10 clock suspend command the clock suspend command is used to interrupt the internal clock of the low power sdram. the command is controlled by the clock enable input, ke, which is high, v ih , in normal access mode. the clock suspend command is issued by driving ke low, v il thus freezing the internal clock and extending data read and write cycles. 4.11 power-down command the power-down command is used to put the device in power-down mode where the operating current is reduced to the standby current. all banks must be precharged and a minimum time of t rp must elapse before issuing the power-down command. 4.12 auto refresh command the auto refresh command is used to put the device in auto refresh mode (see section 3.5: auto refresh ).
commands M65KA128AL 18/53 4.13 self refresh command the purpose of the self refresh command is used to put the device in self refresh mode to retain and refresh the data contained in the low power sdram memory array. in self refresh mode, the low power sdram runs refresh cycles asynchronously. the self refresh cycle is performed according to the extended mode register settings: emr3 to emr4 bits configure the refresh rate at which the memory array is refreshed to perform a temperature compensated self refresh. emr0 to emr2 configure the part of the memory array being refresh (partial array self refresh). 4.14 deep power-down command the deep power-down command is used to switch the low power sdram to deep power- down mode. this mode provides maximum power reduction as it cuts the power of the entire memory array of the device. for more information on how the command is issued and its exit sequence, see section 3.7: deep power-down , figure 25: deep power-down entry ac waveforms , and figure 26: deep power-down exit ac waveforms . table 3. commands (1) command ken-1 ken e ras cas w udqm ldqm a10 a9, a11 a0-a7 ba0- ba1 dq0- dq7 dq8- dq15 mode register set (2) v ih xv il v il v il v il x x op code x x extended mode register set (2) v ih xv il v il v il v il x x op code x x bank (row) active v ih xv il v il v ih v ih x x start row address bank select xx word read/read with auto precharge v ih xv il v ih v il v ih v il v il v il /v ih (3) x start column address bank select output valid upper byte read/read with auto precharge v ih xv il v ih v il v ih v il v ih v il /v ih (3) x start column address bank select hi-z output valid lower byte read/read with auto precharge v ih xv il v ih v il v ih v ih v il v il /v ih (3) x start column address bank select output valid hi-z word write/write with auto precharge v ih xv il v ih v il v il v il v il v il /v ih (3) x start column address bank select input valid upper byte write/write with auto precharge v il v ih v il /v ih (3) x start column address bank select hi-z input valid lower byte write/write with auto precharge v ih v il v il /v ih (3) x start column address bank select input valid hi-z write with auto precharge v ih xv il v ih v il v il v ih x start column address bank select xx
M65KA128AL commands 19/53 precharge all banks v ih xv il v il v ih v il xxv ih xxxx precharge selected bank v ih xv il v il v ih v il xxv il xvxx burst terminate v ih v ih v il v ih v ih v il xx x xxx auto refresh v ih v ih v il v il v il v ih xx x xxx self refresh entry v ih v il v il v il v il v ih xx x xxx self refresh exit (4) v il v ih v ih xxx xx xxxx v il v ih v ih v ih xxxx power-down entry (5)(6) v ih v il v il v ih v ih v ih xx x xxx v ih xxx power-down exit (5)(6) v il v ih v il v ih v ih v ih xx x xxx v ih xxx deep power- down entry v ih v il v il v ih v ih v il xx x xxx deep power- down exit v il v ih xxx x xxx clock suspend entry v ih v il xx xx x x x x x x clock suspend exit v il v ih xx xx x x x x x x data mask / output enable v ih xx x x x v il v il xxxx data mask / output disable v ih xx x x x v ih v ih x x hi-z hi-z 1. x = don?t care v il or v ih . v = valid. 2. ba1 and ba0 must both be driven low, v il , to issue the mode register set command. ba1 and ba0 must be driven high, v ih and low, v il , respectively, to issue the extended mode register set command. 3. to perform read or write operations with autoprecharge, a10 must be held high, v ih . 4. the self refresh mode is exited by asynchronously driving ke from low to high. 5. the power-down mode is exited by asynch ronously driving ke from low to high. 6. banks must be precharged before issuing a power-down command. table 3. commands (1) (continued) command ken-1 ken e ras cas w udqm ldqm a10 a9, a11 a0-a7 ba0- ba1 dq0- dq7 dq8- dq15
register descriptions M65KA128AL 20/53 5 register descriptions 5.1 mode register description the mode register is used to select the cas latency (1, 2 or 3), the burst type (sequential, interleaved), and the burst length (1-, 2-, 4-, 8-word width or full page). it is loaded by issuing a mode register set command that programs a0 to a11 address bits. the values placed on the address lines are then latched into the mode register. ba0-ba1 must be set to ?0?. see table 4: mode register definition , for more details. table 4. mode register definition address bits mode register bit register description value bit description a11-a7 - - 00000 a6-a4 mr6-mr4 cas latency bits 010 2 clock cycles 011 3 clock cycles other configurations reserved a3 mr3 burst type 0 sequential 1 interleaved a2-a0 mr2-mr0 burst length bit 000 1 word (a3 is don?t care) 001 2 words (a3 is don?t care) 010 4 words (a3 is don?t care) 011 8 words (a3 is don?t care) 111 full page if a3 low reserved if a3 high other configurations reserved ba1-ba0 - - 00
M65KA128AL register descriptions 21/53 5.2 extended mode register description the extended mode register is used to program low power self-refresh operation of the device (pasr, ds, tcsr). it is used to select the area of the memory array refreshed during partial array self refresh operations, and the driver strength. it is loaded by issuing a extended mode register set command that programs a0 to a11 address bits. the values placed on the address lines are then latched into the extended mode register. ba0 and ba1 must be set to ?0? and ?1? respectively. see table 5: extended mode register definition , for more details. table 5. extended mode register definition address bits mode register bit register description value bit description a11-a10 - - 00 a9 emr9 auto temperature compensated self refresh (atcsr) 0 enabled 1 reserved a8-a7 - - 00 a6-a5 emr6-emr5 driver strength bits 00 full strength 01 1/2 strength 10 1/4 strength 11 1/8 strength a4-a3 emr4-emr3 00 a2-a0 emr2-emr0 self refresh area bits 000 all banks 001 two banks (ba1=0) 010 one banks (ba0 and ba1 =0) other configurations reserved ba1-ba0 - - 10
maximum rating M65KA128AL 22/53 6 maximum rating stressing the device above the ratings listed in table 6: absolute maximum ratings , may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 6. absolute maximum ratings symbol parameter value unit min max t j junction temperature ?25 90 c t stg storage temperature ?55 125 c v io input or output voltage ?0.5 2.6 v v dd , v ddq supply voltage ?0.5 2.6 v i os short circuit output current 50 ma pd power dissipation 1 w
M65KA128AL dc and ac parameters 23/53 7 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 7: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 3. ac measurement i/o waveform table 7. operating and ac measurement conditions parameter (1)(2) 1. all voltages are referenced to v ss = 0v. 2. t j = ?25 to 90c, f = 1mhz M65KA128AL units min typ max supply voltage (v dd ) 1.65 1.8 1.95 v input/output supply voltage (v ddq ) (3) 3. v ddq must not exceed the level of v dd. 1.65 1.8 1.95 v junction temperature (t j )?25 90c load capacitance (c l )30pf output impedance (z 0 )50 ? input rise/fall time (t r , t f )1ns input high voltage (v ih )1.6v input low voltage (v il )0.2v input and output timing ref. voltages v ddq /2 v output transition timing reference voltages 0.3v ddq 0.7v ddq v ai08009 v ddq i/o timing reference voltage 0v v ddq /2 v ddq output transition timing reference voltage 0v 0.7v ddq 0.3v ddq
dc and ac parameters M65KA128AL 24/53 table 8. ac measurement load circuit table 9. capacitance (1)(2) 1. t j = 25c, f = 1mhz 2. sampled only, not 100% tested. symbol parameter pin M65KA128AL unit min max c i1 input capacitance k2.03.5pf c i2 a0-a11, ba0, ba1, ke, e , ras , cas , w , udqm, ldqm 2.0 3.8 pf c io data i/o capacitance dq0-dq15 6.0 7.5 pf table 10. dc characteristics 1 symbol parameter test condition (1) 1. t j = ?25 to 90c. M65KA128AL unit min max i li input leakage current 0v v in 1.8v ?1 1 a i lo (2) 2. data outputs are disabled. output leakage current 0v v out 1.8v ?1.5 1.5 a v il input low voltage v in = 0v ?0.3 (3) 3. v il may undershoot to -1.0v for less that 5ns. 0.3 v v ih input high voltage v in = 0v 0.8v ddq v ddq + 0.3 (4) 4. v ih may overshoot to 2.6v for less that 5ns. v v ol output low voltage i out = 100a, v in = 0v 0.2 v v oh output high voltage i out = ?100a, v in = 0v v ddq ? 0.2 v ai08008c out c l includes probe capacitance device under test c l z 0
M65KA128AL dc and ac parameters 25/53 table 11. dc characteristics 2 symbol parameter test condition (1) typ unit i dd1 (2) operating current burst length = 1, one bank active t rc t rc (min), i ol = 0ma 36 ma i dd2p standby current in power-down mode ke v il (max), t ck = 15ns 0.6 ma i dd2ps ke v il (max), t ck = input signal stable 0.5 i dd2n standby current in non power-down mode ke v ih (min), e v ih (min), t ck = 15ns input signals are changed once in 30ns 3 ma i dd2ns ke v ih (min), t ck = input signals are stable 1 i dd3p active standby current in power- down mode ke v il (max), t ck = 15ns 1 ma i dd3ps ke v il (max), t ck = 0.8 i dd3n active standby current in non power- down mode ke v ih (min), e v ih (min), t ck = 15ns input signals are changed once in 30ns 15 ma i dd3ns ke v ih (min), t ck = input signals are stable 5 i dd4 (2) burst mode current, cl=2 t ck t ck (min), i ol = 0ma all banks active 35 ma burst mode current, cl=3 52 ma i dd5 (3)(4) auto refresh current, cl=2 t rc1 t rc1 (min) 65 ma auto refresh current, cl=3 i dd6 self refresh current ke 0.2v see table 12. a i dd7 standby current in deep power-down mode see figure 25: deep power-down entry ac waveforms , and figure 26: deep power-down exit ac waveforms . 10 a 1. t j = ?25 to 90c. 2. i dd1 and i dd4 depend on the output loading and cycle rates. all measurements are made with the output open and on condition that the addresses are changed only once during t ck (min.). 3. the minimum value of t rc (ras cycle time for refresh operation) is shown in table 14: asynchronous ac characteristics . 4. i dd5 is measured on condition that the addresses are changed only once during t ck (min.). table 12. self refresh current (i dd6 ) values in normal operating mode (1) temperature 4 banks 2 banks 1 bank unit typ. max. typ. max. typ. max. t j < 40c 150 130 120 a 40c < t j 70c 200 170 150 a 70c t j 90c 600 350 220 a 1. v dd = 1.8v, v ddq = 1.8v, v ss = 0v, ke 0.2v .
dc and ac parameters M65KA128AL 26/53 table 13. synchronous ac characteristics symbol parameter test condition min max unit t ac access time from clock cas latency = 3 7 ns cas latency = 2 9 ns t as address setup time 2 ns t ah address hold time 1 ns t ck clock period cas latency = 3 9.6 ns cas latency = 2 15 ns t cs command setup time 2 ns t ch command hold time 1 ns t chw clock high pulse width 3 ns t clw clock low pulse width 3 ns t cks clock enable setup time 2 ns t cksp clock enable setup time (power-down exit) 2 ns t ckh clock enable hold time 1 ns t ds data input setup time 2 ns t dh data input hold time 1 ns t oh data output hold time 3 ns t olz clock to data output low-z 0 ns t ohz clock to data output high-z cas latency = 3 3 7 ns cas latency = 2 3 9 ns
M65KA128AL dc and ac parameters 27/53 table 14. asynchronous ac characteristics symbol parameter M65KA128AL unit (1) min max t dpl data input valid to precharge command 2 t ck t dal data input valid to bank/row activate command cas latency = 3 2clk + 28.5 ns cas latency = 2 2clk + 30 ns t dqz udqm or ldqm high to data output hi-z 2 t ck t dqm udqm or ldqm high to data input masked 0 t ck t mrd mode register set cycle time 2 t ck t rc ras cycle time 86 ns t rcd delay time, ras active to cas active 28.5 ns t ras ras active time 57 120,000 ns t rp ras precharge time 28.5 ns t rrd delay time, ras active to ras bank active 2 t ck t rc1 auto refresh exit time 105 ns t rc2 (2) self refresh exit time 105 ns t ref refresh time 64 ms t transition time 1 30 ns t wtl delay time, write command to data input 0 t ck 1. the unit t ck is the system clock cycle time. 2. a new command can be issued t rc after the self refresh mode is exited.
dc and ac parameters M65KA128AL 28/53 figure 4. chip enable signal during read, write and precharge 1. the chip enable signal, e , must be issued at a minimum rate with respect to the other signals. 2. burst length = 4 words, latency = 3 clock cycles. 3. raa = address of row a in bank a, caa = address of column a in bank a, qaan= data n read from column a in bank a, daan= data n written to column a in bank a. a10 k hi-z dq n ai09959b w qaa1 qaa2 qaa3 qaa4 dab1 dab2 dab3 dab4 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa low ldqm/ udqm dq0-dq15 high bank/row activate in bank a read from bank a write in bank a precharge bank a low low raa caa cab
M65KA128AL dc and ac parameters 29/53 figure 5. read with precharge ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. a10 dq0-dq15 k tck hi-z dq n ai09934c w dq n+1 dq n+2 dq n+3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ke e ras cas ba0 ba1 address ldqm/ udqm tchw tclw tcks tcs tch tckh tas tah trcd tras trp trc bank/row activate in bank a read from bank a precharge in bank a bank/row activate in bank a tac tolz toh tohz low
dc and ac parameters M65KA128AL 30/53 figure 6. read with auto precharge ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. a10 dq0-dq15 k tck hi-z dq n ai09935c w dq n+1 dq n+2 dq n+3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ke e ras cas ba0 ba1 address ldqm/ udqm tchw tclw tcks tcs tch tckh tas tah trcd tras, trrd trc bank/row activate in bank c read with auto precharge from bank c bank/row activate in bank d bank/row activate in bank c tac tolz toh auto precharge start from bank c tohz low
M65KA128AL dc and ac parameters 31/53 figure 7. clock suspend during burst read ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a, qaan= data n read from column a in bank a. a10 k hi-z ai09947 w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 ke e ras cas ba0 ba1 address low ldqm/ udqm dq0-dq15 bank/row activate in bank a read from bank a raa raa caa qaa1 qaa2 qaa3 qaa4 clock suspended during 1 cycle clock suspended during 2 cycles clock suspended during 3 cycles end of read hi-z
dc and ac parameters M65KA128AL 32/53 figure 8. random column read ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a, qamn= data n read from column m in bank a. a10 k hi-z dq n ai09955 w qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa cab raa raa caa cac low ldqm/ udqm dq0-dq15 high bank/row activate in bank a read from bank a precharge in bank a bank/row activate in bank a read from bank a read from bank a read from bank a
M65KA128AL dc and ac parameters 33/53 figure 9. random row read ac waveforms 1. burst length = 8 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of colu mn a in bank a, qamn= data n read from row m in bank a. a10 k hi-z ai09957 w qba1 qba2 qba5 qba6 qba7 qba8 qaa1 qaa2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address rba rba cba raa rbb rbb cbb caa low ldqm/ udqm dq0-dq15 high bank/row activate in bank b read from bank b precharge in bank b bank/row activate in bank b bank/row activate in bank a read from bank a raa qaa3 qaa4 qaa5 qaa6 qaa7 qba3 qba4 read from bank a
dc and ac parameters M65KA128AL 34/53 figure 10. column interleaved read ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a, qamn= data n read from column m in bank a. a10 k hi-z dq n ai09520b w qaa1 qaa2 qaa3 qaa4 qda1 qda2 qdb1 qdb2 qdc1 qdc2 qab1 qab2 qab3 qab4 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rda rda cda cdc cab cdb high low bank/row activate in bank a read from bank a precharge in bank d read from bank d read from bank d bank/row activate in bank d read from bank d read from bank a precharge in bank a ldqm/ udqm dq0-dq15
M65KA128AL dc and ac parameters 35/53 figure 11. burst column read followed by auto precharge ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a. a10 k hi-z dq n ai09961b w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rda rda cda rdb cdb cab high low bank/row activate in bank a read from bank a bank/row activate in bank d read + auto precharge from bank d bank/row activate in bank d read + auto precharge from bank a read + auto precharge from bank d ldqm/ udqm dq0-dq15 rdb auto precharge from bank d autoprecharge start from bank a
dc and ac parameters M65KA128AL 36/53 figure 12. write ac waveforms 1. burst length = 4 words. a10 k hi-z dq n ai09947 w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 ke e ras cas ba0 ba1 address low ldqm/ udqm dq0-dq15 auto precharge start from bank c bank/row activate in bank c write + auto precharge to bank c bank/row activate in bank b write to bank b bank/row activate in bank c precharge in bank b bank/row activate in bank b tcks tckh tcs, tas tch, tah tds tdh trcd tdal trc trrd trcd tdpl trp tras trc
M65KA128AL dc and ac parameters 37/53 figure 13. byte write ac waveforms 1. burst length = 4 words. hi-z dq8-dq15 bank/row activate in bank d udqm a10 k hi-z ai09963c w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address ldqm dq0-dq7 high read from bank d lower byte read upper byte read upper byte write lower byte write upper byte write read from bank d upper byte read upper byte read tdqz
dc and ac parameters M65KA128AL 38/53 figure 14. mode register set ac waveforms 1. to program the extended mode register, ba0 and ba1 must be set to ?0? and ?1? respectively, and a0 to a11 to the extended mode register data. 2. mr data is the value to be written to the mode register. a10 dq0-dq15 k hi-z ai09948 w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ke e ras cas ba0 ba1 address ldqm/ udqm high tmrd, 2 clock cycles (min) mr data (2) trp precharge all banks mode register set bank/row activate valid
M65KA128AL dc and ac parameters 39/53 figure 15. clock suspend during burst write ac waveforms 1. raa = address of row a in bank a, caa = address of column a in bank a, daan= data n written to column a in bank a. a10 k hi-z ai09950 w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 ke e ras cas ba0 ba1 address low ldqm/ udqm dq0-dq15 bank/row activate in bank a write to bank a raa raa caa daa1 daa2 daa3 clock suspended during 1 cycle clock suspended during 2 cycles clock suspended during 3 cycles daa4
dc and ac parameters M65KA128AL 40/53 figure 16. random column write ac waveforms 1. burst length = 4 words. 2. rda = address of row a in bank d, cda = address of column a in bank d, ddmn= data n written to column m in bank d. a10 k hi-z dq n ai09956b w dda1 dda2 dda3 dda4 ddb1 ddb2 ddc1 ddc2 ddc3 ddc4 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address rda rda cda cdb rdd rdd cdd cdc low ldqm/ udqm dq0-dq15 high bank/row activate in bank d write to bank d precharge in bank d bank/row activate in bank d write to bank d write to bank d write to bank d ddd1 ddd2
M65KA128AL dc and ac parameters 41/53 figure 17. random row write ac waveforms 1. burst length = 8 words. 2. raa = address of row a in bank a, caa = address of column a in bank a, damn= data n written to row m in bank a. a10 k hi-z ai09958 w daa1 daa2 daa5 daa6 daa7 daa8 dda1 dda2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rda rab rab cab cda low ldqm/ udqm dq0-dq15 high bank/row activate in bank a write to bank a precharge in bank a bank/row activate in bank a bank/row activate in bank d write to bank a rda dda3 dda4 dda5 dda6 dda7 daa3 daa4 dda8 write to bank d dab1 dab2
dc and ac parameters M65KA128AL 42/53 figure 18. column interleaved write ac waveforms 1. burst length = 4 words. 2. raa = address of row a in bank a, caa = address of column a in bank a, damn= data n written to column m in bank a. a10 k hi-z dq n ai09521b w daa1 daa2 daa3 daa4 dba1 dba2 dbb1 dbb2 dbc1 dbc2 dab1 dab2 dbb1 dbb2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rba rba cba cbc cab cbb high low bank/row activate in bank a write to bank a write to bank b write to bank b bank/row activate in bank b write to bank b write to bank a precharge in bank a ldqm/ udqm dq0-dq15 cbd dbb3 dbb4 write to bank b precharge in bank b
M65KA128AL dc and ac parameters 43/53 figure 19. burst column write followed by auto precharge ac waveforms 1. burst length = 4 words 2. raa = address of row a in bank a, caa = address of column a in bank a. a10 k hi-z dq n ai09962b w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rda rda cda rdb cdb cab high low bank/row activate in bank a write + auto precharge from bank a bank/row activate in bank d write to bank a write + auto precharge from bank d ldqm/ udqm dq0-dq15 rdb auto precharge start from bank a auto precharge start from bank d bank/row activate in bank d write + auto precharge from bank d
dc and ac parameters M65KA128AL 44/53 figure 20. precharge termination 1. burst length = 8 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a, qaan= data n read from column a in bank a, daan= data n written to column a in bank a. rac rac a10 k hi-z dq n ai09524 w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rab cab high rab ldwm/ udqm write masking dq0-dq15 daa1 daa2 daa3 daa4 daa5 dq n qab1 qab2 qab3 qab4 trcd tras bank/row activate in bank a write to bank a precharge in bank a + write terminated bank/row activate in bank a tdpl trp tras read from bank a precharge in bank a + read terminated bank/row activate in bank a
M65KA128AL dc and ac parameters 45/53 figure 21. power-on sequence 1. mr data and emr data are the values to be written to t he mode register and the extended mode register, respectively. 1 mr data (1) a10 k ai09960b w t0 t1 t2 t3 t4 t5 t6 t9 t10 t11 t12 t13 t8 t14 t15 t16 t17 ke e ras cas ba0 ba1 address ldqm/ udqm t18 t19 t20 hi-z dq0-dq15 bank/row activate t7 t21 precharge all banks cbr auto refresh 1 clock cycle needed 2 refresh cycles needed emr data (1) high level nedeed high mode register set extended mode register set cbr auto refresh tmrd tmrd trp trc1 trc1
dc and ac parameters M65KA128AL 46/53 figure 22. power-down mode and clock masking ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a, qaan= data n read from column a in bank a. qaa1 qaa2 qaa3 qaa4 a10 k ai09951 w t0 t1 t2 t3 t4 t5 t6 t7 t9 t10 t11 t12 t13 t6 t7 t8 t14 t15 t16 t17 ke e ras cas ba0 ba1 address low ldqm/ udqm raa raa caa t18 t19 t20 t21 hi-z dq0-dq15 bank/row activate in bank a read from bank a start of clock masking power-down entry power-down exit active standby end of clock masking precharge in bank a power-down entry power-down exit precharge standby tcksp tcksp
M65KA128AL dc and ac parameters 47/53 figure 23. auto refresh a10 k ai09952c w t0 t1 t2 t3 t4 t5 t6 tn+2 tn+3 tn+4 tn+5 tn+6 tn+1 tm tm+1 tm+2 tm+3 ke e ras cas ba0 ba1 address low ldqm/ udqm tm+4 tm+5 tm+6 hi-z dq0-dq15 precharge bank/row activate read tn tm+7 high auto refresh auto refresh trp trc1 trc1
dc and ac parameters M65KA128AL 48/53 figure 24. self refresh a10 k ai09953b w t0 t1 t2 t3 t4 tn+2 tm tm+1 tn+1 tk ke e ras cas ba0 ba1 address low ldqm/ udqm tk+1 tk+2 tk+3 hi-z dq0-dq15 precharge (optional) tn tk+4 self refresh entry self refresh exit self refresh entry ( or bank/row activate) next clock enable self refresh exit bank/row activate next clock enable trp trc2 trc2
M65KA128AL dc and ac parameters 49/53 figure 25. deep power-down entry ac waveforms 1. ba0, ba1 and address bits a0 to a11 (except a10) are ?don?t care?. a10 dq0-dq15 hi-z k ke e ras cas w ai07720c precharge all banks (optional) deep power-down entry t0 t1 t2 t3 t4 t5 trp
dc and ac parameters M65KA128AL 50/53 figure 26. deep power-down exit ac waveforms 1. mr data and emr data are the values to be written to t he mode register and the extended mode register, respectively. 1 mr data (1) a10 k ai09954c w t0 t1 t2 t3 t4 t5 t6 t9 t10 t11 t12 t13 t8 t14 t15 t16 t17 ke e ras cas ba0 ba1 address ldqm/ udqm t18 t19 t20 hi-z dq0-dq15 deep power-down exit bank/row activate t7 t21 precharge all banks (optional) auto refresh (optional) 1 clock cycle needed 2 refresh cycles needed emr data (1) high level nedeed high 200s mode register set (optional) extended mode register set (optional) auto refresh (optional) tmrd tmrd trp trc1 trc1
M65KA128AL part numbering 51/53 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 15. ordering information scheme example: M65KA128AL 10 w 5 device type m65 = low power sdram delivery form k = wafer form operating voltage, mode, bus width a = v dd = v ddq = 1.8v, standard lpsdram, x16 array organization 128 = 4 banks x 2mbit x 16 option 1 a = one chip enable option 2 l = l die speed class 10 = 10ns package w = unsawn wafer temperature range 5 = ?25 to 90c
revision history M65KA128AL 52/53 9 revision history table 16. document revision history date revision changes 28-nov-2005 1 first issue. 05-jan-2006 2 wafer and die specifications section removed. 28-apr-2006 3 datasheet status updated to full datasheet.
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